US0005965997A19991012US5965997A19991012US5965997US91501997National19970820US9150199719970820USUS19970915019G01R 31382FI20190102EPBHG01R 313835LA20190102EPBHH01M 1048LI20190102EPBHY02E 6010LA20200826EPBGG01R 31/36 20060101A I20051008RMEP 20060101ALI20051008RMEPG01R3136Battery monitoring circuit with storage of charge and discharge accumulation values accessible therefromUS4851839A19890725US5043651A19910827US5341503A19940823US5412323A19950502US5793188A19980811ALWARDI MILADUSMATTHEWS WALLACE EDWARDUSHEACOCK DAVEUSFREEMAN DAVID LOUISUSALWARDI; MILADMATTHEWS; WALLACE EDWARDHEACOCK; DAVEFREEMAN; DAVID LOUISBENCHMARQ MICROELECTRONICSUSBENCHMARQ MICROELECTRONICSBENCHMARQ MICROELECTRONICSUSBENCHMARQ MICROELECTRONICSA battery charge/discharge monitor circuit (10) is operable to be disposed in a battery pack (12) which can be connected to a battery (13). The monitor circuit (10) is operable to be connected to an external CPU (24) or similar system through a single wire communication port (22) for transferring information back and forth. There is also provided an external signal on a line (30) for indicating charge or discharge activity in the monitor circuit (10). The monitor circuit (10) is operable to collect information regarding the amount of charge input to the battery and the length of time that the charge is input to the battery and also the amount of charge that is removed from the battery and the length of time that the charge is removed. This information is stored in a memory block (62) for later access by the external CPU (24). This system also provides offset information to provide some type of compensation for non-linearities of the part. This offset is determined during a calibration operation which operates over a long period of time during a period of inactivity. Regulation circuitry is operable to provide internal regulation to the circuitry with an external JFET (20).